Provide advisement and coordination for RPPG leadership team to drive decision making processes and execution of the strategic business objectives. Develop collaterals (presentations, pre reads, communications) for the CVP on internal and external activities through original contribution and/or collaboration with executives and senior leaders across RPPG. Represent the CV

Drive silicon validation and debug activities. Create plans for IP validation execution. Establish deliverable requirements, milestones, and metrics. Track execution progress. Determine and align schedules with peer groups and internal customers. Implement change control and issue management processes. Coordinate with SOC, platform, and ATE validation teams on plans and e

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Execute on RTL design and coding for various sections of the processor core pipeline and related logic. Collaborate with a team of hardware and software engineers to define the high level architecture. Participate in the definition of microarchitecture of next generation high performance processor cores. Contribute to design verification, synthesis, power reduction, timin

Train and finetune LLMs/LMMs. Improve on the state of the art LLMs/LMMs.. Accelerate the training and inference speed of LLMs/LMMs. Research novel ML techniques and model architectures. Influence the direction of AMD AI platform. Publish your work at top tier venues. PREFERRED EXPERIENCE Experience in developing and debugging in Python. Experience in ML frameworks such as

Performance modeling and analysis of ML training and inference workloads across a single and multiple accelerators. In addition of exploring various tradeoff and design decision. Participate in hardware software co design for future hardware optimization on various ML workloads. Communicate and present the results of the performance analysis and modeling to stakeholders a

Working with Architects and reads documentation to understand features to be implemented and verified Block level test plan creation with the fully understanding of Design Specification UVM block level test bench creation and maintenance Block level test creation in directed and random constraints covering all features usage model and corner cases, for both function and p

Define product features and capabilities, close architecture, and micro architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all feat

Assume ownership in development and/or verification of firmware designed for an embedded microcontroller. Develop and verify firmware in C/C++ Occasional creation of utility software using C++, Perl, Python Work with HW design and verification engineers to verify firmware features Contribute to architecture of hardware, firmware and power management features PREFERRED EXP

We are looking for a Systems Design Engineer to join the System level Test team in San Jose. You will be involved in the silicon life cycle from testing of emulated next generation RTL through to silicon validation. You will have a view of the full system but also will become an expert in certain IP down to the register level. We are looking for someone who can span the r

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Train and finetune LLMs, LMMs, and image/video generation models. Improve on the state of the art LLMs, LMMs, and image/video generation models. Accelerate the training and inference speed of LLMs, LMMs, and image/video generation models. Research novel ML techniques and model architectures. Influence the direction of AMD AI platform. Publish your work at top tier venues.

Manage a team of RTL engineers Technical leadership within an RTL team, and across other core teams Identify bottlenecks and propose new features to improve Floating Point performance. Work with performance modeling team to model and study new features. Identify power and area optimizations, supporting multiple design variants Implement new features in RTL, working with p

The candidate would be responsible for planning, designing, implementing, debugging, and optimizing compiler and SDK/Library for machine learning and 3D graphics hardware IP, as well as developing functional and stress applications. Collaborate with hardware architects and logic designers to solve functional issues, and customer support engineers to help resolve verificat

Some of the expected responsibilities of the candidate will include System level modelling of power IPs, in time and frequency domain, using the models to predict post silicon performance against key metrics. Working with designers in silicon and package and ensure power routing is done to guarantee performance Supply noise analysis at a package and board level and workin